Analog-to-digital convertors (ADCs) may be used in many devices for example, but not limited to, in a Serializer/Deserializer (SerDes) typically used in high speed communications. The ADC samples an analog signal and outputs a digital signal. In a SerDes, the ADC may be used to improve the signal and determine which symbols were transmitted. In some applications the sampling rate may be very high, and therefore time-interleaved ADC is used, whereby multiple ADCs process different parts of the signal in a time-interleaved fashion to accommodate the very high sampling rate. However, time-interleaved ADC may be used for any sampling rate.
For optimal performance, each of the ADCs in the time-interleaved system samples different symbols in the signal at the same phase of each symbol. For example, each symbol is sampled at its peak. Therefore, the phase difference between adjacent samples should be equal. However, due to various impairments, the phase difference may be unequal. This is known as timing/phase skew or timing/phase mismatch. In some time-interleaved ADCs, each symbol may be sampled at more than one point.
Various systems have attempted to correct this mismatch. For example, US Patent Publication 2006/0232460 of Fong-Ching, et al., describes an apparatus and a method for estimating at least one of timing, gain, and offset errors of a time-interleaved ADC. The apparatus has a first ADC, a second ADC, a converter, an estimator, and a compensator. The converter has a Fourier Transform converter and a calculator.
U.S. Pat. No. 7,084,793 to Elbornsson describes a device that estimates time errors in a time interleaved A/D converter system. To this end an output signal (y1, y2, . . . , yM) is fed to a correction device, that is provided to correct the signals with an estimated time error and to produce M signals (z1, z2, . . . , zM). These signals are used in an estimation algorithm device to estimate the time error and the time estimated time errors are then fed to the correction device.